Резюме FPGA designer, ASIC design/verification engineer

Denys M

Должность: FPGA designer, ASIC design/verification engineer
Образование: неполное среднее
Имя: Denys
Фамилия: M
Страна, регион: Австралия, - /согласен на смену жительства/

Адрес: kijev

Заработная плата: 500 USD

Возрост: 47

Телефон:

Факс:

email:

Языки:

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WORK EXPERIENCE:
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10.2004 пїЅ present time. Aldec inc (www.aldec.com) Poland, Gdansk
Senior SW/HW design engineer:
- Leading engineer in memory modeling hardware acceleration project for modern HDL simulators based on Alatek HES boards. System architect, main developer of hardware (VHDL-based inside FPGA) and software cores (C++ based for Win32, Solaris and Linux);
- Leading engineer in software acceleration models project. System architect, main developer;
- Team leader: 1 full-time and up to 2 part-time engineers.

10.2003 пїЅ 10.2004. Aldec inc, Poland, Gdansk
Junior FPGA design engineer:
- Set-associative cache memory core design for Nios-based SoC;
- SDR/DDR SDRAM DIMM controller cores adaptive to different DIMMs for systems based on ARM, Nios, MicroBlaze processors and PRUS multiprocessor system;
- Participation in development and verification of co-verification projects (design of peripheral logic inside FPGA, C programs for ARM and Nios);
- Spelling of the engineering specifications in English.

01.2003 - 04.2003, 06.2003. Aldec inc, training in Poland, Katowice
SQA engineer:
- Excellent and very efficient test base for VHDL, Synopsys Open Vera, System Verilog, Verilog simulator, test automations based on Perl scripts.

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EDUCATION:
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08.1998 - 09.2003. Sevastopol National Technical University (Ukraine). Computer sciences. Master`s degree. Average point is 4.8 from 5.0. (C/C++, DSP, FPGA, HDLs). Implemented projects:
- Weak level signals detection system based on Virtex FPGA;
- Viterbi decoder IP Core, arithmetic encoder core;
- Real time speech recognizing system based on TMS320C6711 processor, implemented in hardware;

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ADDITIONAL SKILLS:
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Languages:
- VHDL/Verilog HDL пїЅ (5 years of logic design and verification experience, excellent knowledge);
- System Verilog, assertion based verification concepts - (1 year, average knowledge);
- C/C++ (OOP, Unix and Win32 programming experience) пїЅ (5 years, excellent knowledge);
- Assembler x86 пїЅ (2 years, excellent knowledge);
- Perl - (2 years, good knowledge) + basic knowledge of TCL;

Programming components (libraries):
- SystemC core library - (average knowledge);
- STL - (3 years, excellent knowledge);
- VHPI/PLI - (1 year, average knowledge);
- MFC, Win32 API, DirectX7.0, Unix API - (2 years, average knowledge);

Design tools:
- Modern FPGA design tools (Modelsim, Synplify Pro, ISE, Quartus II, SOPC Builder, EDK etc) пїЅ (5 years, excellent knowledge);
- Matlab/Simulink пїЅ (1 year, average knowledge);
- TI Code Composer Studio пїЅ (1 year, average knowledge);
- g++, MS Visual Studio - (5 years, excellent knowledge);

DSP
пїЅ (1 year, strong DSP mathematical background, good knowledge of audio, video and image processing algorithms, JPEG, MPEG, noise-cancellation);

Hardware:
- Modern Xilinx and Altera FPGA families - (5 years, excellent knowledge of architecture);
- PCI, PCI Express пїЅ (good knowledge);
- Avalon, OPB, ASB, I2C, AHB пїЅ (2 years, excellent knowledge);
- Modern DRAM/SRAM memory interfaces пїЅ (2 years, excellent knowledge);
- ARM, Nios - (basic knowledge);
- Intel x86 architecture - (2 years, excellent knowledge);

OS Windows (98/NT/2000/XP), OS Linux, MS Office.

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LANGUAGES:
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English (good), Polish (average), German (basic), Russian (native), Ukrainian (average).

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Additional information:
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Creative, executive, responsible, willing to learn new technologies, standalone/team work experience.

добавлено 2005-06-28 показано 1651 раз

Должность:	FPGA designer, ASIC design/verification engineer
Образование:	неполное среднее
Имя:	Denys
Фамилия:	M
Страна, регион:	Австралия, - /согласен на смену жительства/
Адрес:	kijev
Заработная плата:	500 USD
Возрост:	47
Телефон:
Факс:
email:
Языки:
--------- WORK EXPERIENCE: --------- 10.2004 пїЅ present time. Aldec inc (www.aldec.com) Poland, Gdansk Senior SW/HW design engineer: - Leading engineer in memory modeling hardware acceleration project for modern HDL simulators based on Alatek HES boards. System architect, main developer of hardware (VHDL-based inside FPGA) and software cores (C++ based for Win32, Solaris and Linux); - Leading engineer in software acceleration models project. System architect, main developer; - Team leader: 1 full-time and up to 2 part-time engineers. 10.2003 пїЅ 10.2004. Aldec inc, Poland, Gdansk Junior FPGA design engineer: - Set-associative cache memory core design for Nios-based SoC; - SDR/DDR SDRAM DIMM controller cores adaptive to different DIMMs for systems based on ARM, Nios, MicroBlaze processors and PRUS multiprocessor system; - Participation in development and verification of co-verification projects (design of peripheral logic inside FPGA, C programs for ARM and Nios); - Spelling of the engineering specifications in English. 01.2003 - 04.2003, 06.2003. Aldec inc, training in Poland, Katowice SQA engineer: - Excellent and very efficient test base for VHDL, Synopsys Open Vera, System Verilog, Verilog simulator, test automations based on Perl scripts. --------- EDUCATION: --------- 08.1998 - 09.2003. Sevastopol National Technical University (Ukraine). Computer sciences. Master`s degree. Average point is 4.8 from 5.0. (C/C++, DSP, FPGA, HDLs). Implemented projects: - Weak level signals detection system based on Virtex FPGA; - Viterbi decoder IP Core, arithmetic encoder core; - Real time speech recognizing system based on TMS320C6711 processor, implemented in hardware; --------- ADDITIONAL SKILLS: --------- Languages: - VHDL/Verilog HDL пїЅ (5 years of logic design and verification experience, excellent knowledge); - System Verilog, assertion based verification concepts - (1 year, average knowledge); - C/C++ (OOP, Unix and Win32 programming experience) пїЅ (5 years, excellent knowledge); - Assembler x86 пїЅ (2 years, excellent knowledge); - Perl - (2 years, good knowledge) + basic knowledge of TCL; Programming components (libraries): - SystemC core library - (average knowledge); - STL - (3 years, excellent knowledge); - VHPI/PLI - (1 year, average knowledge); - MFC, Win32 API, DirectX7.0, Unix API - (2 years, average knowledge); Design tools: - Modern FPGA design tools (Modelsim, Synplify Pro, ISE, Quartus II, SOPC Builder, EDK etc) пїЅ (5 years, excellent knowledge); - Matlab/Simulink пїЅ (1 year, average knowledge); - TI Code Composer Studio пїЅ (1 year, average knowledge); - g++, MS Visual Studio - (5 years, excellent knowledge); DSP пїЅ (1 year, strong DSP mathematical background, good knowledge of audio, video and image processing algorithms, JPEG, MPEG, noise-cancellation); Hardware: - Modern Xilinx and Altera FPGA families - (5 years, excellent knowledge of architecture); - PCI, PCI Express пїЅ (good knowledge); - Avalon, OPB, ASB, I2C, AHB пїЅ (2 years, excellent knowledge); - Modern DRAM/SRAM memory interfaces пїЅ (2 years, excellent knowledge); - ARM, Nios - (basic knowledge); - Intel x86 architecture - (2 years, excellent knowledge); OS Windows (98/NT/2000/XP), OS Linux, MS Office. --------- LANGUAGES: --------- English (good), Polish (average), German (basic), Russian (native), Ukrainian (average). --------- Additional information: --------- Creative, executive, responsible, willing to learn new technologies, standalone/team work experience.
добавлено 2005-06-28	показано 1651 раз